1. Field of the Invention
The present invention relates to a semiconductor device comprising a metal insulator semiconductor (MIS) transistor formed on a semiconductor layer on an insulating film, and a method of manufacturing the same.
2. Description of the Related Art
For a long time now, a substrate having a single-crystal silicon film formed on an insulating film called the silicon-on-insulator (SOI) substrate, has been the subject of studies since it makes high-performance semiconductor devices. With recent developments in wafer techniques, discussions in the application of the SOI substrate have been increasing.
FIGS. 21 and 22 show a plan view of a semiconductor device according to a conventional NMOS transistor. FIG. 23 is a sectional view of the semiconductor device taken along the line XXIII—XXIII line of FIGS. 21 and 22 in which wiring, contacts, and interlayer insulation films have been omitted.
FIGS. 21-23 shows an SOI substrate 14. The SOI substrate 14 is formed of a buried oxide film 12 formed on a support 11 and a semiconductor layer 13 formed on the buried oxide film 12. Within the semiconductor layer 13, the active region 16 exists in which a p−-type substrate-potential controlling layer 17 is formed. On the substrate-potential controlling layer 17, a gate electrode 20 is formed via a gate insulating film 18 in a predetermined pattern. In the surface of the active region 16, N+-type source and drain regions 29, 29′ are formed adjacent to the gate electrode 20, whereas in the active region 16 facing the source and drain regions 29, 29′, a P+-type body contact region 31 is formed.
The gate electrode 20 shown in FIG. 21 is formed in a shape of straight line extending from body region to a body extension region, whereas, the gate electrode 20 shown in FIG. 22 has a first portion 20a in a line shape on the body region, and a second portion 20b linked and formed at a right angle to the first portion 20a. The width of the second portion 20b is D2.
In the semiconductor devices mentioned above, the term “body region” refers to the region in which the channel between the source and drain regions 29, 29′ is formed. The term “body extension region” refers to a region in contact with the body region at its side boundary making a right angle with a gate-length direction and excluding the source and drain regions 29, 29′. The body contact region 31 is a high-concentration region in contact with the body extension region at its side boundary making a right angle with the gate length direction for making a good contact with an upper electrode.
In the transistor described in the above, the potential of the body region can be controlled by applying a voltage (potential) to the body contact region 3, making it possible to overcome the problem of “substrate-floating effect” associated with the SOI substrate. Also, if the same potential is applied to both the gate electrode 20 and the body region, the threshold voltage of the transistor decreases as the voltage of the gate electrode 20 increases, increasing the drain current. Accordingly, a transistor circuit with a high-performance can be obtained compared to that formed on a bulk substrate.
The substrate floating effect produces adverse effects such as pass-gate leak, history effect, and decreased source-to-drain breakdown voltage. The pass-gate leak used herein refers to the phenomenon in which a current flows between the source and drain when input (source) is switched from a power supply voltage to a ground potential despite the pass gate circuit consisting of an NMOS transistor being turned off (gate is connected to a ground potential). The history effect refers to the phenomenon where the switching speed of an inverter circuit varies depending upon the frequency of the input pulse. These adverse effects will cause circuit malfunction. If an attempt is made to avoid the circuit malfunction, the operation speed of the circuit will decrease.
In the transistor shown in FIG. 21, a PN junction is formed by arranging the high-concentration N-type source and drain regions 29, 29′ in a close contact with the high-concentration P-type contact region 31. To maintain the breakdown voltage of the PN junction, these two regions must be arranged at a predetermined distance d (e.g., about 0.3 μm). On the other hand, the source and drain regions 29, 29′ and the body contact region 31 are formed by doping N-type and P-type impurity ions through respective openings formed locally on resist patterns. In this manufacturing method, an additional distance s (e.g., about 0.3 μm) must be maintained, taking the alignment tolerance between two resist patterns into account. Accordingly, the distance D1 (d+s) between the source and drain regions 29, 29′ and the body contact region 31 must be set at the long distance.
However, if the distance D1 is increased, the area occupied by the transistor increases, making the chip size bigger and increasing the manufacturing cost. Also, increasing the distance D1 increases the parasitic resistance, making it difficult to control the potential of the body region and so causing problems due to the substrate floating effect mentioned previously.
In the transistor shown in FIG. 21, the source and drain regions 29, 29′, the P−-type substrate-potential controlling layer 17, and the body contact region 31 are formed continuously. Because of this, if a silicide were formed on the surface of the semiconductor layer 13 in a self-alignment manner (i.e., if a salicide is formed), a short circuit would occur between these portions. Therefore, the salicide cannot be formed. However, in a transistor having a gate length of 0.1 μm or less, unless a salicide is formed, the current driving of the transistor will be considerably reduced due to the parasitic resistance between the source and drain, decreasing the switching speed of the transistor circuit.
On the other hand, in the transistor shown in FIG. 22, the source and drain regions 29, 29′ and the body contact region 31 are formed by doping N-type and P-type impurity ions, respectively by using the second portion 20b of the gate electrode 20 as a mask for the ion doping. In this manufacturing method, the gate electrode 20, the N-type source and drain regions 29, 29′, and the body contact region 31 can be formed in a self-alignment manner such that the high-concentration N-type source and drain regions 29, 29′ and high-concentration P-type body contact region 31 are not positioned adjacent to each other. Accordingly, the distance D2 can be reduced by about 0.3 μm compared with that of the transistor shown in FIG. 21, minimizing the increase in area and parasitic resistance. In addition, a salicide can be formed, thus the transistor of FIG. 22 is now generally used as a standard transistor with body contact even for the gate length of 0.1 μm or less.
However, there is still a problem in this case. Since a parasitic gate capacitance is generated in a region 100 in which the second portion 20b of the gate electrode 20 faces the substrate potential controlling layer 17, the switching speed of the transistor circuit decreases.